Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
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United States of America Patent
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Jun 4, 2013
Grant Date -
Mar 22, 2012
app pub date -
Sep 17, 2010
filing date -
Sep 17, 2010
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Abstract
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
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