Cycle time reduction in data preparation
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United States of America Patent
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Jun 4, 2013
Grant Date -
Feb 14, 2013
app pub date -
Aug 11, 2011
filing date -
Aug 11, 2011
priority date (Note) -
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Abstract
The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
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