Bond pad connection to redistribution lines having tapered profiles
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United States of America Patent
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Jun 11, 2013
Grant Date -
Jul 7, 2011
app pub date -
Mar 17, 2011
filing date -
Oct 9, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.
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