Resonant clock and interconnect architecture for digital devices with multiple clock networks
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United States of America Patent
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Jun 11, 2013
Grant Date -
Sep 1, 2011
app pub date -
May 9, 2011
filing date -
May 23, 2007
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Abstract
A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
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