CMOS circuit with dynamic parasitic net pulldown circuit
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United States of America Patent
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Jun 11, 2013
Grant Date -
Jan 3, 2013
app pub date -
Jul 1, 2011
filing date -
Jul 1, 2011
priority date (Note) -
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Abstract
A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates.
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