Multiplexer circuit with load balanced fanout characteristics
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United States of America Patent
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Jun 11, 2013
Grant Date -
Aug 2, 2012
app pub date -
Jan 27, 2011
filing date -
Jan 27, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.
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