SOI switch enhancement
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United States of America Patent
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Jun 11, 2013
Grant Date -
N/A
app pub date -
Sep 13, 2010
filing date -
Sep 11, 2009
priority date (Note) -
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Abstract
The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.
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