System for retaining state data

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United States of America Patent

PATENT NO 8462533
APP PUB NO 20110216578A1
SERIAL NO

13107591

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.

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Patent Owner(s)

Patent OwnerAddress
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITEDSINGAPORE

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Penzes, Paul Newport Beach, US 31 306

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