Surrogate circuit for testing an interface

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United States of America Patent

PATENT NO 8464107
APP PUB NO 20110320894A1
SERIAL NO

12824783

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Abstract

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A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The interface logic facilitates testing of the interface logic by attempting to perform the function on the surrogate circuit. The interface logic may be a memory interface, and the surrogate circuit may be a memory circuit that is a smaller and simpler replica of an external memory die. The surrogate circuit allows the interface logic to be tested before the semiconductor die is physically coupled to the external device, for exampled in a three dimensional (3D) integrated circuit (IC).

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Patent Owner(s)

Patent OwnerAddress
QUALCOMM INCORPORATED5775 MOREHOUSE DRIVE SAN DIEGO CA 92121-1714

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chun, Christopher Kong Yee Austin, US 31 138
Srinivasan, Anand San Diego, US 159 9444

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