Word line activation in memory devices
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United States of America Patent
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Jun 18, 2013
Grant Date -
Feb 23, 2012
app pub date -
Oct 31, 2011
filing date -
Jul 10, 2007
priority date (Note) -
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Abstract
Memory devices and methods, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines.
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