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Abstract

A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed by DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate transition data bits. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the transition data bits. The weighted threshold is calculated from at least one of the prior-received DFE detected data bits. In one embodiment, the DFE detection may also be dependent on an effective delay (λ) of the DFE circuit in relation to the received signal baud-period, T.

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First Claim