Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
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United States of America Patent
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Jun 18, 2013
Grant Date -
Jun 23, 2011
app pub date -
Dec 22, 2009
filing date -
Dec 22, 2009
priority date (Note) -
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Abstract
A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
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