Laminate capacitor stack inside a printed circuit board for electromagnetic compatibility capacitance
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United States of America Patent
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Jul 23, 2013
Grant Date -
May 17, 2012
app pub date -
Nov 16, 2010
filing date -
Nov 16, 2010
priority date (Note) -
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Abstract
An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.
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