Architecture for operating resonant clock network in conventional mode
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United States of America Patent
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Aug 6, 2013
Grant Date -
Apr 14, 2011
app pub date -
Oct 12, 2010
filing date -
Oct 12, 2009
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Abstract
An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.
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