Wafer scale chip scale packaging of vertically integrated MEMS sensors with electronics
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United States of America Patent
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Aug 13, 2013
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app pub date -
May 8, 2008
filing date -
May 8, 2008
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Abstract
In a method and system in accordance with the present invention, solder balls are added on top of vertically integrated MEMS with CMOS by using wafer scale fabrication compatible with existing chip scale packaging capabilities. In the present invention, both the MEMS and the CMOS dies are fabricated in equal dimensions. On the MEMS level, silicon islands are defined by DRIE etching to be bonded on top of CMOS pads. These conducting silicon islands later provide electrical connections between the CMOS pads and the conducting traces that lead to solder balls on top.
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