Changing abstraction level of portion of circuit design during verification

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8510693
APP PUB NO 20120317526A1
SERIAL NO

13469944

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Abstract

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A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist.

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Patent Owner(s)

  • FUJITSU LIMITED;SOCIONEXT INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kikuta, Hideo Yokohama, JP 1 3
Sato, Hiroyuki Kawasaki, JP 469 5044

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