Double data rate operation in an integrated circuit
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United States of America Patent
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Aug 20, 2013
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N/A
app pub date -
Oct 2, 2008
filing date -
Oct 2, 2008
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Abstract
In various embodiments, an integrated circuit may include a number of elements configured to operate at the rate of a supplied clock signal (Single Data Rate, or SDR), and further include other elements configured to operate at twice the rate of the clock signal (Double Data Rate, or DDR). In some embodiments, the circuit may further include elements configured to transform signals between SDR and DDR. In various embodiments, the elements may select a first input during a first phase of a clock signal and select a second input during a second phase of a clock signal to provide a double data rate output. In some embodiments, the elements may form a double data rate portion of the integrated circuit that receives two bits per clock cycle and provides two output bits per clock cycle.
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