SPE software instruction cache
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Aug 20, 2013
Grant Date -
Jun 30, 2011
app pub date -
Dec 29, 2009
filing date -
Dec 29, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
An application thread executes a direct branch instruction that is stored in an instruction cache line. Upon execution, the direct branch instruction branches to a branch descriptor that is also stored in the instruction cache line. The branch descriptor includes a trampoline branch instruction and a target instruction space address. Next, the trampoline branch instruction sends a branch descriptor pointer, which points to the branch descriptor, to an instruction cache manager. The instruction cache manager extracts the target instruction space address from the branch descriptor, and executes a target instruction corresponding to the target instruction space address. In one embodiment, the instruction cache manager generates a target local store address by masking off a portion of bits included in the target instruction space address. In turn, the application thread executes the target instruction located at the target local store address accordingly.
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