Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same
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United States of America Patent
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Sep 3, 2013
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N/A
app pub date -
Apr 2, 2009
filing date -
Apr 2, 2009
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Abstract
In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.
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