Methods for testing a memory embedded in an integrated circuit
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United States of America Patent
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Sep 10, 2013
Grant Date -
Jan 17, 2013
app pub date -
Sep 13, 2012
filing date -
Mar 31, 2009
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Abstract
A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
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