Optimizing computation of minimum cut in graphs with grid topology
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United States of America Patent
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Sep 10, 2013
Grant Date -
Mar 7, 2013
app pub date -
Sep 6, 2011
filing date -
Sep 6, 2011
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Abstract
Approaches for optimizing computation of minimum cut or maximum flow on graphs comprising a plurality of nodes and edges with grid-like topologies are disclosed. Embodiments exploit the regular structure of input graphs to reduce the memory bandwidth—a main bottleneck of popular max-flow/min-cut algorithms based on finding augmenting paths on a residual graph (such as Ford-Fulkerson [1956] or Boykov-Kolmogorov [2004]). Disclosed embodiments allow more than 200% speed-up without sacrificing optimality of the final solution, which is crucial for many computer vision and graphics applications. Method and system embodiments replace standard linked list representation of general graphs with a set of compact data structures with blocked memory layout that enables fixed ordering of edges and implicit branchless addressing of nodes. The embodiments are orthogonal to other optimizations such as parallel processing or hierarchical methods and can be readily plugged into existing min-cut/max-flow computation systems to further improve their performance.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
CZECH TECHNICAL UNIVERSITY IN PRAGUE FACULTY OF ELECTRICAL ENGINEERING | TECHNICKA 2 166 27 PRAHA 6 |
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- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Jamri{hacek, over (s)}ka Ond{hacek over (r)}ej | Praha, CZ | 1 | 3 |
Sýkora, Daniel | Praha, CZ | 10 | 31 |
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