Method and system for implementing top down design and verification of an electronic design

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8539405
APP PUB NO 20120311513A1
SERIAL NO

13561900

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Abstract

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Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kurshan, Robert P New York, US 15 264
McMillan, Kenneth L Berkeley, US 9 105

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