Method for packaging circuits
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United States of America Patent
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Oct 15, 2013
Grant Date -
Mar 15, 2012
app pub date -
Nov 17, 2011
filing date -
May 6, 2003
priority date (Note) -
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Abstract
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
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