Multithreaded, superscalar scheduling in a traffic manager of a network processor

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United States of America Patent

PATENT NO 8565250
APP PUB NO 20120020371A1
SERIAL NO

13251091

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Abstract

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Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an associated queue. The queue has a corresponding level M, with a corresponding parent scheduler at each of M−1 levels in the scheduling hierarchy, where M is less than or equal to N. In a single scheduling cycle, a parent scheduler selects a child node to transmit one or more tasks, and the child node responds whether the scheduling is accepted, and if so, with a number of tasks for scheduling. Starting at the parent scheduler and iteratively repeating at each level until reaching the root scheduler, statistics corresponding to the selected node are updated. Output packets corresponding to the scheduled tasks are transmitted, thereby achieving a superscalar task scheduling throughput.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nemawarkar, Shashank Austin, US 33 445
Sonnier, David Austin, US 19 219
Sundararaman, Balakrishnan Cedar Park, US 23 325

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