Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiP

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United States of America Patent

PATENT NO 8601422
APP PUB NO 20100115487A1
SERIAL NO

12341152

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Abstract

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An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhattacharya, Utpal Noida, IN 7 93
Choudhary, Parag Noida, IN 4 55
Jain, Abha Greater Noida, IN 7 30
Tripathi, Alok Noida, IN 13 132

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