Apparatus and method for disabling a microprocessor that provides for a secure execution mode
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United States of America Patent
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Dec 10, 2013
Grant Date -
Nov 26, 2009
app pub date -
Oct 31, 2008
filing date -
May 24, 2008
priority date (Note) -
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Abstract
An apparatus including a microprocessor, a system memory, and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that transfers program control to one of a plurality of event handlers within the secure application program. The system memory has non-secure application programs stored therein. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where the secure application program is encrypted when stored in the secure non-volatile memory, and where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
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