Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8615644
APP PUB NO 20110208949A1
SERIAL NO

12708791

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Abstract

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A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION;NXP USA, INC.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bruce, Becky Leander, US 2 42
Frazier, Giles R Austin, US 109 1030
Frey, Bradly G Austin, US 47 921
Gala, Kumar K Austin, US 6 119
May, Cathy Ossining, US 42 996
Snyder, Michael D Cedar Park, US 70 1252
Whisenhunt, Gary Leander, US 2 42
Xenidis, James Carmel, US 45 654

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