High reliability processor system
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United States of America Patent
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Dec 24, 2013
Grant Date -
Oct 18, 2012
app pub date -
Apr 18, 2011
filing date -
Apr 18, 2011
priority date (Note) -
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Abstract
A method of testing the integrity of microprogramming within a computer processor employs a test calculation designed to exercise instructions and to reveal errors in those instructions. The problem of testing instructions using the very instructions which may possibly be corrupt is addressed by developing a signature passed from instruction to instruction providing a low likelihood of a false positive outcome. A time-out system is used in the evaluation of the test calculation to capture a wide variety of other pathological operating conditions.
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