Byte-accurate scheduling in a network processor

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United States of America Patent

PATENT NO 8619787
APP PUB NO 20120020210A1
SERIAL NO

13250927

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Abstract

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Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. Each scheduler determines one or more tasks to schedule from a given queue based on a default packet size of the packet corresponding to the task. The corresponding packet data is read from a shared memory, and, at each corresponding parent scheduler up to the root scheduler, an actual size of the packet data is updated. Scheduling weights of each corresponding parent scheduler are updated based on the actual size of the packet data.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sonnier, David Austin, US 19 219
Sundararaman, Balakrishnan Cedar Park, US 23 326

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