Semiconductor device having plural banks
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United States of America Patent
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Jan 14, 2014
Grant Date -
May 31, 2012
app pub date -
Nov 23, 2011
filing date -
Nov 26, 2010
priority date (Note) -
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Abstract
A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.
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