GaN high voltage HFET with passivation plus gate dielectric multilayer structure
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United States of America Patent
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Jan 21, 2014
Grant Date -
Jun 6, 2013
app pub date -
Dec 1, 2011
filing date -
Dec 1, 2011
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Abstract
A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
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