Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients
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United States of America Patent
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Jan 21, 2014
Grant Date -
Nov 14, 2013
app pub date -
Jul 27, 2012
filing date -
May 9, 2012
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Abstract
A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop.
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