Write driver circuit for MRAM, MRAM and layout structure thereof
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United States of America Patent
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Jan 21, 2014
Grant Date -
Oct 11, 2012
app pub date -
Aug 27, 2011
filing date -
Apr 6, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A write driver circuit for a magnetic random access memory includes a memory cell array including a plurality of magnetic memory cells in which a pair of magnetic memory cells adjacent to each other in a direction of a bit line share a source line, and each magnetic memory cell is connected between the bit line and the source line. The write driver circuit includes a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line according to a write enable signal and a data signal.
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