Method for fabrication of crystalline diodes for resistive memories
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United States of America Patent
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Jan 28, 2014
Grant Date -
Aug 18, 2011
app pub date -
Apr 29, 2011
filing date -
Feb 7, 2008
priority date (Note) -
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Abstract
The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
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