Transistor structure for improved static control during formation of the transistor
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United States of America Patent
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Feb 25, 2014
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app pub date -
Sep 23, 2010
filing date -
Sep 23, 2010
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Abstract
A method of forming a shadow mask vapor deposited transistor includes shadow mask vapor depositing a semiconductor segment. An electrically conductive drain contact is shadow mask vapor deposited on a first part of the semiconductor segment and a first insulator is shadow mask vapor deposited on the drain contact. An electrically conductive source contact is shadow mask vapor deposited on a second part of the semiconductor segment spaced from the drain contact and a second insulator is shadow mask vapor deposited on the source contact. A third insulator is shadow mask vapor deposited over at least part of each of the first and second insulators and the semiconductor segment between the drain contact and the source contact. An electrically conductive gate contact is shadow mask vapor deposited on the third insulator and in spaced relation to the semiconductor segment between the drain contact and the source contact.
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