Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
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United States of America Patent
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Feb 25, 2014
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N/A
app pub date -
Apr 5, 2012
filing date -
Oct 3, 2011
priority date (Note) -
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Abstract
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.
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