MOS transistor, manufacturing method thereof, and semiconductor device
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United States of America Patent
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Apr 22, 2014
Grant Date -
Aug 22, 2013
app pub date -
Feb 7, 2013
filing date -
Feb 7, 2013
priority date (Note) -
Withdrawn
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Abstract
A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.
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