Pattern-sensitive coding of data for storage in multi-level memory cells

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United States of America Patent

PATENT NO 8665642
APP PUB NO 20110286267A1
SERIAL NO

13140345

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Abstract

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A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Haukness, Brent Steven Monte Sereno, US 38 380
Linstadt, John Eric Palo Alto, US 148 321
Rychlik, Bohuslav San Diego, US 93 1656
Woo, Steven C Saratoga, US 71 895

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