Simultaneous and selective partitioning of via structures using plating resist

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United States of America Patent

PATENT NO 8667675
APP PUB NO 20080301934A1
SERIAL NO

12190551

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Abstract

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Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

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Patent Owner(s)

Patent OwnerAddress
SANMINA-SCI CORPORATION2700 NORTH FIRST STREET SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dudnikov,, Jr George San Jose, US 9 107

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