Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
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United States of America Patent
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Mar 25, 2014
Grant Date -
Apr 28, 2011
app pub date -
Oct 26, 2010
filing date -
Oct 26, 2009
priority date (Note) -
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Abstract
The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
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