Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
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United States of America Patent
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Mar 25, 2014
Grant Date -
Dec 9, 2010
app pub date -
Jun 3, 2009
filing date -
Jun 3, 2009
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Abstract
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.
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