Circuit for the optimization of the programming of a flash memory
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United States of America Patent
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Mar 25, 2014
Grant Date -
Jan 5, 2012
app pub date -
Jun 28, 2011
filing date -
Jun 30, 2010
priority date (Note) -
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Abstract
A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. The memory device includes a program circuit configured to receive at least one second data word, and, for each second data word, send a program current in parallel to discriminated memory cells based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate the at least one second data word from the first data word. The number of discriminated memory cells of the second data word is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit.
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