Method and apparatus for minimizing within-die variations in performance parameters of a processor

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United States of America Patent

PATENT NO 8683098
APP PUB NO 20110238868A1
SERIAL NO

12748922

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Abstract

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Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Johnson, Luke A Queen Creek, US 39 424
Srikanth, Adhiveeraraghavan Folsom, US 11 44
Yun, Wenjun Lincoln, US 7 10

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