Cache and method for cache bypass functionality

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United States of America Patent

PATENT NO 8683139
APP PUB NO 20080104329A1
SERIAL NO

11554827

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Abstract

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A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

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Patent Owner(s)

  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gaither, Blaine D Ft. Collins, US 60 1372
Knebel, Patrick Ft. Collins, US 29 521

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