Technique and apparatus for identifying cache segments for caching data to be written to main memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 25, 2014
Issued Date -
N/A
app pub date -
Aug 21, 2012
filing date -
May 30, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully