Double data rate clock gating
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United States of America Patent
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Apr 1, 2014
Grant Date -
Apr 4, 2013
app pub date -
Sep 30, 2011
filing date -
Sep 30, 2011
priority date (Note) -
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Abstract
Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.
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