Semiconductor device and structure
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United States of America Patent
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Apr 1, 2014
Grant Date -
Apr 4, 2013
app pub date -
Oct 2, 2011
filing date -
Oct 2, 2011
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Abstract
An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.
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