Methods, apparatuses, and circuits for bimodal disable circuits
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United States of America Patent
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Apr 8, 2014
Grant Date -
Jan 2, 2014
app pub date -
Aug 23, 2013
filing date -
Dec 21, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
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