Semiconductor device with wiring substrate including lower conductive pads and testing conductive pads
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United States of America Patent
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Apr 15, 2014
Grant Date -
Jun 21, 2012
app pub date -
Mar 1, 2012
filing date -
Sep 12, 2007
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Abstract
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.
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