Controlling time stamp counter (TSC) offsets for mulitple cores and threads

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United States of America Patent

PATENT NO 8700943
APP PUB NO 20110154090A1
SERIAL NO

12644989

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Abstract

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In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dixon, Martin G Portland, US 135 1467
Parthasarathy, Rajesh S Hillsboro, US 32 633
Shrall, Jeremy J Portland, US 49 818

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